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-- Company: 
-- Engineer:
--
-- Create Date:   13:40:57 05/19/2011
-- Design Name:   
-- Module Name:   C:/Users/Geoff/Documents/Degree/CSSE2000/Vcode/theproject/alu_test.vhd
-- Project Name:  theproject
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: proc_alu
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
use work.proc_package.ALL;


ENTITY alu_test IS
END alu_test;
 
ARCHITECTURE behavior OF alu_test IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT proc_alu
    PORT(
         clk : IN  std_logic;
         rst : IN  std_logic;
         en : IN  std_logic;
         mode : IN  PROC_ALU_MODE;
         status_in : IN  std_logic_vector(7 downto 0);
         a : IN  std_logic_vector(7 downto 0);
         b : IN  std_logic_vector(7 downto 0);
         result : OUT  std_logic_vector(7 downto 0);
         status_out : OUT  std_logic_vector(7 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal clk : std_logic := '0';
   signal rst : std_logic := '0';
   signal en : std_logic := '0';
   signal mode : PROC_ALU_MODE := NONE;
   signal status_in : std_logic_vector(7 downto 0) := (others => '0');
   signal a : std_logic_vector(7 downto 0) := (others => '0');
   signal b : std_logic_vector(7 downto 0) := (others => '0');

 	--Outputs
   signal result : std_logic_vector(7 downto 0);
   signal status_out : std_logic_vector(7 downto 0);

   -- Clock period definitions
   constant clk_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: proc_alu PORT MAP (
          clk => clk,
          rst => rst,
          en => en,
          mode => mode,
          status_in => status_in,
          a => a,
          b => b,
          result => result,
          status_out => status_out
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ms.
      --wait for 100 ms;	

      wait for clk_period*10;

      mode <=ALU_AND_MODE;
		a <= "10000000";
		b <= "10111100";
		en <='1'; 
		wait for clk_period;
		en<='0';
      wait;
   end process;

END;
